SHAKTI is an open-source initiative led by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras. The objective of SHAKTI is to create production-grade processors, fully integrated System on Chips (SoCs), development boards, and software platforms based on SHAKTI. The RISC-V ISA is the foundation for SHAKTI processors. Depending on the manufacturing foundry, the CPUs are built using either 22 nm FinFET or 180 nm CMOS technology. "Base Processors," "Multi-Core Processors," and "Experimental Processors" are the three basic categories into which they have been divided. The E and C-classes are the first set of indigenous processors aimed at Internet of Things (IoT), Embedded and Desktop markets.
E-class processors
The E-class, designed for low-power and low-computer applications, are 32/64 bit microcontrollers capable of implementing all RISC-V ISA extensions. The E-class is a three-stage pipeline with an operational frequency of less than 200 MHz on silicon. It is capable of running real-time operating systems like FreeRTOS, Zephyr and eChronos. Market segments for E-class processors include smart cards, IoT devices, motor controls, and robotic platforms.
E-arty35T is a SoC based on E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral (SPI), 2 Universal Asynchronous Receiver Transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse Width Modulators (PWM), 32 General Purpose Input Output (GPIO) pins (of which the upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Xilinx analog-to-digital (X-ADC).
E-arty35T
- E-arty35Tis a SoC based on SHAKTI E class.
- E-arty35Tis supported on Artix 7 35T board.
- It has an abridged version of 32 bit E class. It includes I, M, A and C.
AXI
The ARM Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications include the Advanced eXtensible Interface (AXI), which is a parallel high-performance, synchronous, high-frequency, multi-master, multi-slave communication interface primarily intended for on-chip communication. The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices.
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